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Table 4–1 AlphaServer 1000 Fault Detection and Correction

Component Fault Detection/Correction Capability

KN22A Processor Module

DECchip 21064 and 21064A

microprocessors

Contains error detection and correction (EDC) logic for

data cycles. There are check bits associated with all data

entering and exiting the 21064(A) microprocessor. A single-

bit error on any of the four longwords being read can be

corrected (per cycle). A double-bit error on any of the four

longwords being read can be detected (per cycle).

Backup cache (B-cache) EDC check bits on the data store, and parity on the tag

address store and tag control store.

Memory Subsystem

Memory SIMMs EDC logic protects data by detecting and correcting data

cycle errors. A single-bit on any of the four longwords can

be corrected (per cycle). A double-bit error on any of the

four longwords being read can be detected (per cycle).

System Motherboard

SCSI Controller SCSI data parity is generated.

EISA-to-PCI bridge chip PCI data parity is generated.

4.1.1 Machine Check/Interrupts

The exceptions that result from hardware system errors are called machine

check/interrupts. They occur when a system error is detected during the

processing of a data request. There are four types of machine check/interrupts

related to system events:

1. Processor machine check (SCB 670)

2. System machine check (SCB 660)

3. Processor-corrected machine check (SCB 630)

4. System-corrected machine check (SCB 620)

During the error handling process, errors are ﬁrst handled by the appropriate

PALcode error routine and then by the associated operating system error handler.

The causes of each of the machine check/interrupts are as follows. The system

control block (SCB) vector through which PALcode transfers control to the

operating system is shown in parentheses.

4–2 Error Log Analysis

1 2 ... 59 60 61 62 63 64 65 66 67 68 69 ... 181 182

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Alpha 1000 User's Guide Page 64